1 ps8418c 08/02/02 1 2 3 av cc 4 clk_out clk_in gnd fb_in 8 7 6 5 agnd v cc s product pin configuration logic block diagram 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI6C2402 product features ? 2x clk_in on clk_out ? high-performance phase-locked-loop clock distribution for networking, atm, 100/134 mhz registered dimm synchronous dram modules for server/workstation/ pc applications ? zero input-to-output delay ? low jitter: cycle-to-cycle jitter 100ps max. ? on-chip series damping resistor at clock output drivers for low noise and emi reduction ? operates at 3.3v v cc ? wide range of clock frequencies ? package: plastic 8-pin soic package (w) phase-locked loop clock driver product description the PI6C2402 features a low-skew, low-jitter, phase-locked loop (pll) clock driver. by connecting the feedback clk_out output to the feedback fb_in input, the propagation delay from the clk_in input to any clock output will be nearly zero. the PI6C2402 provides 2x clk_in on clk_out output. application if the system designer needs more than 16 outputs with the features just described, using two or more zero-delay buffers such as pi6c2509q, and pi6c2510q, is likely to be impractical. the device- to-device skew introduced can significantly reduce the perfor- mance. pericom recommends the use of a zero-delay buffer and an eighteen output non-zero-delay buffer. as shown in figure 1, this combination produces a zero-delay buffer with all the signal characteristics of the original zero-delay buffer, but with as many outputs as the non-zero-delay buffer part. for example, when combined with an eighteen output non-zero delay buffer, a system designer can create a seventeen-output zero-delay buffer. figure 1. this combination provides zero-delay between the reference clocks signal and 17 outputs 17 zero delay buffer PI6C2402 reference clock signal clk_out feedback 18 output non-zero delay buffer v control input se c r u o s t u p t u on w o d t u h s l l p 1l l pn 0n i _ k l cy clk_in fb_in s pll clk_out 2 8-pin w
PI6C2402 phase-locked loop clock driver 2 ps8418c 08/02/02 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 e m a n n i pr e b m u n n i pe p y tn o i t p i r c s e d n i _ k l c1i t u p n i k c o l c m u r t c e p s d a e r p s s w o l l a n i _ k l c . t u p n i k c o l c e c n e r e f e r v a c c 2r e w o p. r e w o p g o l a n a d n g a3d n u o r g. d n u o r g g o l a n a t u o _ k l c4o d n a n i _ k l c f o s e i p o c w e k s - w o l s e d i v o r p t u p t u o e h t . t u p t u o k c o l c . r o t s i s e r g n i p m a d - s e i r e s d e d d e b m e n a s a h s5i o t d e p p a r t s s i s n e h w . s e s o p r u p t s e t r o f l l p e h t s s a p y b o t d e s u s i s . s t u p n i l o r t n o c . s t u p t u o e c i v e d e h t o t y l t c e r i d d e r e f f u b s i n i _ k l c d n a d e s s a p y b s i l l p , d n u o r g d n g6 d n u o r g. d n u o r g v c c 7r e w o p. y l p p u s r e w o p n i _ b f8i . l l p l a n r e t n i e h t o t l a n g i s k c a b d e e f e h t s e d i v o r p n i _ b f . t u p n i k c a b d e e f pin functions l o b m y sr e t e m a r a p. n i m. x a ms t i n u v i e g n a r e g a t l o v t u p n i5 . 0 ?v c c 5 . 0 + v v o e g n a r e g a t l o v t u p t u o5 . 0 ?v c c 5 . 0 + c d _ i ve g a t l o v t u p n i c d5 . 0 ?0 . 5 + c d _ o it n e r r u c t u p t u o c d 0 0 1a m r e w o pt t a n o i t a p i s s i d r e w o p m u m i x a m a 5 5 = o r i a l l i t s n i c0 . 1w t g t s e r u t a r e p m e t e g a r o t s5 6 ?0 5 1 o c absolute maximum ratings (over operating free-air temperature range, see note 1) note: 1. stress beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. recommended operating conditions l o b m y sr e t e m a r a pe r u t a r e p m e t. n i m. x a ms t i n u v c c e g a t l o v y l p p u sl a i c r e m m o c0 . 36 . 3 v e g a t l o v y l p p u sl a i r t s u d n i5 3 1 . 35 6 4 . 3 v h i e g a t l o v t u p n i l e v e l h g i h0 . 2 v l i e g a t l o v t u p n i l e v e l w o l 8 . 0 v i e g a t l o v t u p n i0v c c t a e r u t a r e p m e t r i a - e e r f g n i t a r e p ol a i c r e m m o c00 7 c o e r u t a r e p m e t r i a - e e r f g n i t a r e p ol a i r t s u d n i0 4 ?5 8
PI6C2402 phase-locked loop clock driver 3 ps8418c 08/02/02 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 electrical characteristics (over recommended operating free-air temperature range) ac specifications timing requirements (over recommended ranges of supply voltage and operating free-air temperature, c l = 25pf) l o b m y sr e t e m a r a pn o i t i d n o c t s e t. n i m. p y t. x a ms t i n u f k c o l c y c n e u q e r f k c o l cl a i c r e m m o c5 24 3 1 z h m y c n e u q e r f k c o l cl a i r t s u d n i5 20 0 1 d i y c e l c y c y t u d k c o l c t u p n i0 40 6% p u r e w o p r e t f a e m i t n o i t a z i l i b a t s 1s m t p r e t t i j t u o h t i w r o r r e e s a h p ) 3 ( n i _ k l c z h m 6 6 d n a z h m 0 0 1 t a0 5 1 ?0 5 1 + s p j te l c y c - o t - e l c y c , r e t t i jz h m 6 6 d n a z h m 0 0 1 t a0 0 1 ?0 0 1 + e l c y c y t u d5 45 5% t r v 0 . 2 o t v 4 . 0 , e m i t - e s i r 0 . 1 s n t f v 4 . 0 o t v 0 . 2 , e m i t - l l a f 1 . 1 note: 3. this switching parameter is guaranteed by design. l o b m y sn o i t i d n o c t s e te r u t a r e p m e tv c c . n i m. p y t. x a ms t i n u i c c v i v = c c i ; d n g r o o 0 = ) 2 ( l a i c r e m m o cv 6 . 30 1 a v i v = c c i ; d n g r o o 0 = ) 2 ( l a i r t s u d n iv 5 6 4 . 30 1 c i v i v = c c d n g r o v 3 . 3 4 f p c o v o v = c c d n g r o6 i h o v t u o v 4 . 2 = 2 1 ? a m v t u o v 0 . 2 = 8 1 ? i l o v t u o v 8 . 0 =8 1 v t u o v 5 5 . 0 =2 1 note: 2. continuous output current
PI6C2402 phase-locked loop clock driver 4 ps8418c 08/02/02 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com 8-pin plastic soic (w) package e d o c g n i r e d r oe m a n e g a k c a pe p y t e g a k c a pe g n a r g n i t a r e p o w 2 0 4 2 c 6 i p8 wc i o s l i m - 0 5 1 n i p - 8l a i c r e m m o c i w - 2 0 4 2 c 6 i p8 wc i o s l i m - 0 5 1 n i p - 8l a i r t s u d n i ordering information .0040 .0098 seating plane .013 .020 .050 bsc .016 .0075 .0098 1 8 .0099 .0196 0-8? .050 .149 .157 x.xx x.xx denotes dimensions in millimeters 3.78 3.99 .189 .196 4.80 5.00 1.27 .016 .026 1.35 1.75 .2284 .2440 5.80 6.20 0.406 0.660 0.330 0.508 0.10 0.25 0.40 1.27 0.19 0.25 0.25 0.50 x 45? .053 .068 ref
|
